The present invention generally relates to data processing systems, and more specifically to selectively simultaneously writing a same value to a block of registers.
Computer processors typically include in their instruction sets instructions for changing processor state. For example, many computer architectures include instructions to change from user mode to supervisory mode, and back. Indeed, without this sort of instruction, it is highly problematic whether architecture can do an adequate job in protecting one user from another, or the operating system from users.
In a modern operating system (OS), there are well-defined tasks that must be accomplished when an operating system dispatches user tasks and programs to execute, and when the operating system receives control back after such execution. Some of these tasks including loading and storing general-purpose registers and segment registers.
Some architectures, especially Reduced Instruction Set Computer (RISC) architectures, utilize long, often repeated, sequences of code to load and store these general purpose and segment registers. As this function is repeated whenever control is transferred to or received from a user program, this approach of utilizing long, often repeated, sequences of code can be quite costly. For that reason, specialized instructions have been added to some architectures to expedite this entire process. For example, the GCOS 8 architecture, owned by the assignee of this invention, includes a CLIMB instruction utilized to change from supervisory mode to user mode, and back. The CLIMB family of instructions performs all actions necessary to change from supervisory mode to user mode, and back in a single instruction.
Unfortunately, execution of such complex state changing instructions as the CLIMB can be quite expensive in terms of processor cycles required for execution. This is especially important in high volume transaction environments where it is necessary to switch back and forth, to and from supervisory mode to user mode quite often. It would thus be extremely useful if the number of computer cycles could be reduced when executing a complex state change instruction.
One place where a significant amount of time is spent during execution of complex state change instructions is in loading and restoring all of the registers required. This is typically done in a serial fashion, loading or storing one register at a time. Indeed, many modern computer processor architectures include instructions to load or store entire banks of registers. For example, the Unisys 1100/2200 computer architecture includes load and store multiple register instructions. Similarly, the IBM/Motorola PowerPC architecture contains Load Multiple Word (lmw) and Store Multiple Word (stwm) instructions for loading and storing entire banks of registers. However, as noted above, these instructions invariably operate in a serial fashion, loading or storing one register at a time. It would thus be advantageous for a computer architecture to provide a mechanism for overlapping, or parallelizing at least some register loading and/or storing.